OP5110 - PCI Virtex2 pro FPGA

High-Density Digital I/O, High-Precision Event Capture and High-Speed PWM Output 32-bit

The OP5110 I/O interface from Opal-RT Technologies allows the incorporation of FPGA technologies, for high-speed, high-density digital I/O in real-time models, in RT-LAB simulation clusters. Based on an ultra-high-density reconfigurable module using Xilinx Virtex-II Pro Platform FPGAs, the OP5110 allows the inclusion of up to 128 channels of Digital I/O, operating at up to 100 MHz cycle frequencies, with a pulse resolution down to 10 ns.

This means that you can capture or generate events between the simulation time steps to an accuracy of 1 µs to incorporate very precise timing into the model for, say, IC engine ignition sparks or IGBT switching in an electronic power converter. An effective precisI/On better than 1 µs can be obtained when combining the FPGA event detection with specialized real-time interpolation algorithms included in the RT-EVENTS block set

• Event detectors and generators, with a resolution of 10 ns resolution, able to capture of events between simulation time steps
• Capable of generating PWM outputs at up to 15 kHz cycle frequency
• Multiple event generation & detection in one simulation cycle
• Library of drag-and-drop blocks for Simulink
• Easy interface Simulink blocks to generate arbitrary waveforms programmable on-the-fly at each model time step using RT-EVENTS block set (see "Pulse GeneratI/On with FPGA and RT- EVENTS in Simulink").
• Static Digital Output option (pulse output at beginning of each time step)
• The FPGA IP core is stored in flash memory; users do not need FPGA development tool
• Each group can be configured as input or output
• Up to 128 software-configurable I/O lines, in groups of 8 lines
• Fast DMA burst transfer between the FPGA memory and the model memory (30 ns per event with the PCI bus)

SignalWire - High-Speed Serial Data Interface

• Very fast serial link (up to 1.25 Gbits/s)
• Use for linking Target Processors at higher performance than FireWire
• Use for linking remote sensors to Target PCs by carrying out the conversion locally sending the data over the link
• Use for very large I/O counts, connecting to a single PCI board
• High priority messages with 200 ns latency
• Event detectors and generators, with a resolution of 10 ns, able to capture or events between simulation time steps

The OP5110 supports PCI Bus 32 bit, 33 MHz compliant interfaces. Features include up to 132 Mb/s bus bandwidth via PCI bus interface, choice of on-board or host configuration, and 128 user-configurable I/O pins.

It also includes a new innovative high-speed real-time networking interface that allows you to connect your distributed processors together to operate at faster cycle times than ever before! Called SignalWire, this real-time link takes advantage of the raw FPGA power to deliver up to 1.25 Gbit/s transfer rates, with a latency of 200 ns. That's about two times the rate of FireWire and less than 10% of the latency!

Furthermore, the OP5110 provides a platform for additional data acquisition and signal conditioning modules that will allow high frequency analog signals to be captured into, and generated out of, the real-time simulation.  Typical minimum model step size is around 30us to 50us. Minimum step size depends on model complexity and target hardware configuration. Please contact us for more details.

The platform is configured using the supplied library of Simulink blocks that allow the user to implement the DI/O, event capture, event generation, and PWM I/O capabilities in the real-time model without coding. It even includes a block for rotation-angle-synchronized events, such as engine spark.